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Rev. 1.1
FLASH MEMORY
CMOS
8M (1M x 8/512K x 16) BIT
CSR2930800BA-90
s DESCRIPTION
The CSR2930800BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K words of 16 bits each. TheCSR2930800BA are offered in a 48-pin TSOP(I), 44-pin SOP, and 48-ball FBGA packages. These devices are designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard CSR2930800BA offer access times 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The CSR2930800BA are pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The CSR2930800BA are programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the devices automatically time the erase pulse widths and verify proper cell margin. (Continued)
s PRODUCT LINE UP
Part No. Ordering Part No. Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) (Continued) VCC = 3.0 V
+0.6 V -0.3 V
CSR2930800BA -90 90 90 35
CSR2930800BA-90
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.) The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The CSR2930800BA are erased when shipped from the factory. The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. The CSR2930800BA memories electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.
s PACKAGES
48-pin Plastic TSOP (I)
Marking Side
48-pin Plastic FBGA
48-pin Plastic SCSP
(WLP-48P-M03)
(FPT-48P-M19)
(BGA-48P-M12)
(WLP-48P-M03)
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CSR2930800BA-90
s FEATURES
* Single 3.0 V read, program, and erase Minimizes system level power requirements * Compatible with JEDEC-standard commands Uses same software commands as E2PROMs * Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP(I) (Package suffix: PFTN - Normal Bend Type) 48-ball FBGA (Package suffix: PBT) 48-ball SCSP (Package suffix: PW) * Minimum 100,000 program/erase cycles * High performance 90 ns maximum access time * Sector erase architecture One 8K word, two 4K words, one 16K word, and fifteen 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase * Boot Code Sector Architecture B = Bottom sector * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Sector protection Hardware method disables any combination of sectors from program or erase operations * Sector Protection set function by Extended sector Protect command * Temporary sector unprotection Temporary sector unprotection via the RESET pin *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
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CSR2930800BA-90
s PIN ASSIGNMENTS
TSOP(I) A15 A14 A13 A12 A11 A10 A9 A8 N.C. N.C. WE RESET N.C. N.C. RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ 15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0
CSR2930800BA Normal Bend
(FPT-48P-M19)
(Continued)
4
CSR2930800BA-90
(Continued)
FBGA
(Top View)
Marking side
A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6
BGA-48P-M02
A1 B1 C1 D1 E1 F1 G1 H1
A3 A4 A2 A1 A0 CE OE VSS
A2 B2 C2 D2 E2 F2 G2 H2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A3 B3 C3 D3 E3 F3 G3 H3
RY/BY N.C. A18 N.C. DQ2 DQ10 DQ11 DQ3
A4 B4 C4 D4 E4 F4 G4 H4
WE RESET N.C. N.C. DQ5 DQ12 VCC DQ4
A5 B5 C5 D5 E5 F5 G5 H5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
A6 B6 C6 D6 E6 F6 G6 H6
A13 A12 A14 A15 A16 BYTE DQ15/A-1 VSS
SCSP (Top View) Marking side
A6 A3 A5 A7 A4
B6 A4 B5 A17 B4
C6 A2 C5 A6 C4 A18 C3
D6 A1 D5 A5 D4 N.C D3 N.C D2 A11 D1 A15
E6 A0 E5 DQ0 E4 DQ2 E3
F6 CE F5 DQ8 F4
G6 OE G5
H6 VSS H5
DQ9 DQ1 G4 H4
RY/BY N.C A3 B3
DQ10 DQ11 DQ3 F3 G3 H3 DQ4 H2
WE RESET N.C A2 A9 A1 A13 B2 A8 B1 A12 C2 A10 C1 A14
DQ5 DQ12 VCC E2 F2 G2
DQ7 DQ14 DQ13 DQ6 E1 A16 F1 G1 H1
BYTE DQ15/A-1 VSS
(WLP-48P-M02)
5
CSR2930800BA-90
s PIN DESCRIPTION
Pin name A-1, A0 to A18 DQ0 to DQ15 CE OE WE RY/BY RESET BYTE VSS VCC N.C. Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Unprotection Selects 8-bit or 16-bit mode Device Ground Device Power Supply No Internal Connection Function
6
CSR2930800BA-90
s BLOCK DIAGRAM
RY/BY Buffer V CC V SS DQ 0 to DQ 15 RY/BY
Erase Voltage Generator
Input/Output Buffers
WE BYTE RESET State Control Command Register Program Voltage Generator CE OE Chip Enable Output Enable Logic STB Data Latch
STB
Y-Decoder
Y-Gating
Low V CC Detector
Timer for Program/Erase
Address Latch
X-Decoder
Cell Matrix
A0 to A18 A-1
s LOGIC SYMBOL
A-1 19 A0 to A18 DQ 0 to DQ 15 CE OE WE RESET BYTE RY/BY 16 or 8
7
CSR2930800BA-90
s DEVICE BUS OPERATION
CSR2930800BA User Bus Operations Table (BYTE = VIH) Operation Auto-Select Manufacturer Code * Auto-Select Device Code *1 Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Protection *2, *4 Verify Sector Protection *2, *4 Temporary Sector Unprotection Reset (Hardware)/Standby
1
CE L L L H L L L L X X
OE L L L X H H VID L X X
WE H H H X H L
A0 L H A0 X X A0 L
A1 L L A1 X X A1 H H X X
A6 L L A6 X X A6 L L X X
A9 VID VID A9 X X A9 VID VID X X
DQ0 to DQ15 Code Code DOUT High-Z High-Z DIN X Code X High-Z
RESET H H H H H H H H VID L
H X X
L X X
= Pulse input. See "s CHARACTERISTICS" for voltage levels. DC Legend: L = VIL, H = VIH, X = VIL or VIH, *1: Manufacturer and device codes may also be accessed via a command register write sequence. See "CSR2930800BA Standard Command Definitions Table". *2: Refer to "7. Sector Protection" in s FUNCTIONAL DESCRIPTIONS. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V 10% *5: It is also used for the extended sector protection. CSR2930800BA User Bus Operations Table (BYTE = VIL) Operation Auto-Select Manufacturer Code *1 Auto-Select Device Code * Read *3 Standby Output Disable Write (Program/Erase) Enable Sector Protection *2, *4 Verify Sector Protection * *
2, 4 1
CE L L L H L L L L X X
OE L L L X H H VID L X X
WE H H H X H L
DQ15/ A-1 L L A-1 X X A-1 L
A0 L H A0 X X A0 L L X X
A1 L L A1 X X A1 H H X X
A6 L L A6 X X A6 L L X X
A9 VID VID A9 X X A9 VID VID X X
DQ0 to DQ7 RESET Code Code DOUT High-Z High-Z DIN X Code X High-Z H H H H H H H H VID L
H X X
L X X
Temporary Sector Unprotection *5 Reset (Hardware)/Standby
= Pulse input. See "s CHARACTERISTICS" for voltage levels. DC Legend: L = VIL, H = VIH, X = VIL or VIH, *1: Manufacturer and device codes may also be accessed via a command register write sequence. See "CSR2930800BA Standard Command Definitions Table". *2: Refer to "7. Sector Protection" in s FUNCTIONAL DESCRIPTIONS. *3: WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4: VCC = 3.3 V 10% *5: It is also used for the extended sector protection. 8
CSR2930800BA-90
CSR2930800BA Sector Protection Verify Autoselect Codes Table Type Manufacture's Code Device Code CSR2930800BA Byte Word A12 to A18 X X Sector Addresses A6 VIL VIL VIL A1 VIL VIL VIH A0 VIL VIH VIL A-1*1 VIL VIL X VIL Code (HEX) 04h 5Bh 225Bh 01h*2
Sector Protection *1: A-1 is for Byte mode.
*2: Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
Expanded Autoselect Code Table Type Manufacturer's Code (B) Device CSR2930800BA Code (W) Sector Protection (B): Byte mode (W): Word mode HI-Z: High-Z
Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
04h
A-1/0
0 0 0
0 1 0
0 0 0
0 0 0
0 0 0
0 1 0
0 0 0
0 0 0
0 1 1 0
0 0 0 0
0 1 1 0
0 1 1 0
1 0 0 0
0 1 1 0
0 1 1 1
5Bh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0
225Bh
0
A-1/0
01h
9
CSR2930800BA-90
CSR2930800BA Standard Command Definitions Table Command Sequence
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
Bus Write Cycles Req'd
First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXh 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh F0h AAh AAh AAh AAh AAh -- 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h -- 55h 55h 55h 55h 55h -- 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh -- F0h 90h A0h 80h 80h -- RA -- PA 555h AAAh 555h AAAh -- RD -- PD AAh AAh -- -- -- -- 2AAh 555h 2AAh 555h -- -- -- -- 55h 55h -- -- -- -- 555h AAAh SA -- -- -- -- 10h 30h
Read/Reset
1 3 3 4 6 6
Read/Reset
Autoselect
Program
Chip Erase
Sector Erase
Sector Erase Suspend Sector Erase Resume
Erase can be suspended during sector erase with Addr. ("H" or "L"). Data (B0h) Erase can be resumed after suspend with Addr. ("H" or "L"). Data (30h)
Notes: * Address bits A11 to A18 = X = "H" or "L" for all address commands except or Program Address (PA) and Sector Address (SA) * Bus operations are defined in "CSR2930800BA User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" . * RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. * RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of WE. * The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A0 to A10 Byte Mode: AAAh or 555h to addresses A-1 and A0 to A10 * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. * Command combinations not described in "CSR2930800BA Standard Command Definitions Table" and "CSR2930800BA Extended Command Definitions Table" are illegal.
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CSR2930800BA-90
CSR2930800BA Extended Command Definitions Table Command Sequence Set to Fast Mode Fast Program*1 Reset from Fast Mode *1 Extended Sector Protect*2 Word Byte Word Byte Word 2 Byte Word Byte 4 XXXh 60h SPA 60h SPA 40h SPA SD XXXh Bus Write Cycles Req'd 3 2 First Bus Write Cycle Addr 555h AAAh XXXh XXXh XXXh 90h XXXh Data AAh A0h Second Bus Write Cycle Addr 2AAh 555h PA XXXh F0h*3 -- -- -- -- Data 55h PD Third Bus Write Cycle Addr 555h AAAh -- Data 20h -- Fourth Bus Read Cycle Addr -- -- Data -- --
SPA : Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD : Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1: This command is valid while Fast Mode. *2: This command is valid while RESET=VID. *3: This data "00h" is also acceptable.
11
CSR2930800BA-90
s FLEXIBLE SECTOR-ERASE ARCHITECTURE
* One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes * Individual-sector, multiple-sector, or bulk-erase capability * Individual or multiple-sector protection is user definable.
(x8) 64K byte
(x16)
FFFFFh 7FFFFh EFFFFh 77FFFh 64K byte DFFFFh 6FFFFh 64K byte CFFFFh 67FFFh 64K byte BFFFFh 5FFFFh 64K byte AFFFFh 57FFFh 64K byte 9FFFFh 64K byte 8FFFFh 64K byte 7FFFFh 64K byte 6FFFFh 64K byte 5FFFFh 64K byte 4FFFFh 64K byte 3FFFFh 64K byte 2FFFFh 64K byte 1FFFFh 64K byte 0FFFFh 32K byte 07FFFh 8K byte 05FFFh 8K byte 03FFFh 16K byte 00000h 00000h CSR2930800BA Sector Architecture 01FFFh 02FFFh 03FFFh 07FFFh 0FFFFh 17FFFh 1FFFFh 27FFFh 2FFFFh 37FFFh 3FFFFh 47FFFh 4FFFFh
12
CSR2930800BA-90
Sector Address Table (CSR2930800BA) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X X X X X X X X X A13 0 1 1 X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X Address Range (x8) 00000h to 03FFFh 04000h to 05FFFh 06000h to 07FFFh 08000h to 0FFFFh 10000h to 1FFFFh 20000h to 2FFFFh 30000h to 3FFFFh 40000h to 4FFFFh 50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to FFFFFh Address Range (x16) 00000h to 01FFFh 02000h to 02FFFh 03000h to 03FFFh 04000h to 07FFFh 08000h to 0FFFFh 10000h to 17FFFh 18000h to 1FFFFh 20000h to 27FFFh 28000h to 2FFFFh 30000h to 37FFFh 38000h to 3FFFFh 40000h to 47FFFh 48000h to 4FFFFh 50000h to 57FFFh 58000h to 5FFFFh 60000h to 67FFFh 68000h to 6FFFFh 70000h to 77FFFh 78000h to 7FFFFh
13
CSR2930800BA-90
s FUNCTIONAL DESCRIPTION
1. Read Mode
The CSR2930800BA have two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after power-up, it is necessary to input hardware reset or change CE pin from "H" or "L"
2. Standby Mode
There are two ways to implement the standby mode on the CSR2930800BA devices, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC 0.3 V. Under this condition the current consumed is less than 5 A. The device can be read with standard access time (tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = "H". When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS 0.3 V (CE = "H" or "L"). Under this condition the current is consumed is less than 5 A. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode the outputs are in the high impedance state, independent of the OE input.
3. Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of CSR2930800BA data. This mode can be used effectively with an application requested low power consumption such as handy terminals. To activate this mode, CSR2930800BA automatically switch themselves to low power mode when CSR2930800BA addresses remain stably during access fine of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 A (CMOS Level). Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically and CSR2930800BA read-out the data for changed addresses.
4. Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.
5. Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the devices. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON'T CARES except A0, A1, A6, and A-1. (See "CSR2930800BA Sector Protection Verify Autoselect Codes Table" ins DEVICE BUS OPERATION.) The manufacturer and device codes may also be read via the command register, for instances when the CSR2930800BA are erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "CSR2930800BA Standard Command Definitions Table" (s DEVICE BUS OPERATION). (Refer to "2. Autoselect Command" in s COMMAND DEFINITIONS.) 14
CSR2930800BA-90
Byte 0 (A0 = VIL) represents the manufacturer's code (04h) and (A0 = VIH) represents the device identifier code (CSR2930800BA = 5Bh for x8 mode; CSR2930800BA = 225Bh for x16 mode). These two bytes/words are given in "CSR2930800BA Sector Protection Verify Autoselect Codes Table" and "Expanded Autoselect Code Table" (s DEVICE BUS OPERATION). All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See "CSR2930800BA User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in s DEVICE BUS OPERATION.)
6. Write
Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
7. Sector Protection
The CSR2930800BA feature hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming equipment at the user's site. The devices are shipped with all sectors unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V), CE = VIL, and A6 = VIL. The sector addresses (A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. "CSR2930800BA Standard Command Definitions Table" and "CSR2930800BA Extended Command Definitions Table" in s DEVICE BUS OPERATION define the sector address for each of the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See "13. AC Waveforms for Sector Protection Timing Diagram" in s SWITCHING WAVEFORMS and "5. Sector Protection Algorithm" in s FLOW CHART for sector protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" code at device output DQ0 for a protected sector. Otherwise the devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON'T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A18, A17, A16, A15, A14, A13, and A12) are the desired sector address will produce a logical "1" at DQ0 for a protected sector. See "CSR2930800BA Sector Protection Verify Autoselect Codes Table" and "Expanded Autoselect Code Table" in sDEVICE BUS OPERATION for Autoselect codes.
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CSR2930800BA-90
8. Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the CSR2930800BA devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again. See "14. Temporary Sector Unprotection Timing Diagram" in s SWITCHING WAVEFORMS and "6. Temporary Sector Unprotection Algorithm" in s FLOW CHART.
9. RESET Hardware Reset
The CSR2930800BA devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 s after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See "9. RESET/RY/BY Timing Diagram" in s SWITCHING WAVEFORMS for the timing diagram. Refer to "8. Temporary Sector Unprotection" for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) cannot be used.
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CSR2930800BA-90
s COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. "CSR2930800BA Standard Command Definitions Table" in s DEVICE BUS OPERATION defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ0 to DQ7 and DQ8 to DQ15 bits are ignored.
1. Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the command register contents are altered. The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
2. Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the devices reside in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h for x16(XX02h for x8) returns the device code (CSR2930800BA = 5Bh for x8 mode; CSR2930800BA = 225Bh for x16 mode). (See "CSR2930800BA Sector Protection Verify Autoselect Codes Table" and "Expanded Autoselect Code Table" in s DEVICE BUS OPERATION.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit. Sector state (protection or unprotection) will be informed by address XX02h for x16 (XX04h for x8). Scanning the sector addresses (A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical "1" at device output DQ0 for a protected sector. The programming verification should be perform margin mode on the protected sector. (See "CSR2930800BA User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in sDEVICE BUS OPERATION.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and also to write the Autoselect command during the operation, execute it after writing Read/Reset command sequence.
17
CSR2930800BA-90
3. Byte/Word Programming
The devices are programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (See "Hardware Sequence Flags Table".) Therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still "0". Only erase operations can convert "0"s to "1"s. FLOW CHART illustrates the Embedded ProgramTM Algorithm using "1. Embedded ProgramTM Algorithm" in s typical command strings and bus operations.
4. Chip Erase
Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is "1" (See "8. Write Operation Status".) at which time the device returns to read the mode. Chip Erase Time; Sector Erase Time x All sectors + Chip Program Time (Preprogramming) FLOW CHART illustrates the Embedded EraseTM Algorithm using typical "2. Embedded EraseTM Algorithm" in s command strings and bus operations.
5. Sector Erase
Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data=30h) is latched on the rising edge of WE. After time-out of 50 s from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing the six bus cycle operations on "CSR2930800BA Standard Command Definitions Table" in s DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 s otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 s from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs 18
CSR2930800BA-90
within the 50 s time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see "12. DQ3", Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to "8. Write Operation Status" for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 18). Sector erase does not require the user to program the devices prior to erase. The devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50 s time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is "1" (See "8. Write Operation Status".) at which time the devices return to the read mode. Data polling must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] x Number of Sector Erase FLOW CHART illustrates the Embedded EraseTM Algorithm using typical "2. Embedded EraseTM Algorithm" in s command strings and bus operations.
6. Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are DON'T CARES when writing the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 20 s to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/ BY output pin and the DQ7 bit will be at logic "1", and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See "13. DQ2".) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
19
CSR2930800BA-90
7. Extended Command
(1) Fast Mode CSR2930800BA has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to "8. Embedded ProgramTM Algorithm for Fast Mode" in "s FLOW CHART" Extended algorithm.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to "8. Embedded ProgramTM Algorithm for Fast Mode" in "s FLOW CHART" Extended algorithm.) (3) Extended Sector Protection In addition to normal sector protection, the CSR2930800BA has Extended Sector Protection as extended function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector protect command (60h). A sector is typically protected in 150 s. To verify programming of the protection circuitry, the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical "1" at device output DQ0 will produce for protected sector in the read operation. If the output data is logical "0", please repeat to write extended sector protect command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH.
8. Write Operation Status
Hardware Sequence Flags Table Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended Mode (Non-Erase Suspended Sector) Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Embedded Erase Algorithm Time Limits Erase Erase Suspend Program Suspended Mode (Non-Erase Suspended Sector) DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle *1 Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 0 1 0 Data 0 0 1 0 DQ2 1 Toggle Toggle Data 1 *2 1 N/A N/A
*1: Performing successive read operations from any address will cause DQ6 to toggle. *2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. Notes: * DQ0 and DQ1 are reserve pins for future use. * DQ4 is internal use only. 20
CSR2930800BA-90
9. DQ7 Data Polling
The CSR2930800BA devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in "3. Data Polling Algorithm" (s FLOW CHART). For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the CSR2930800BA data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant of time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See "Hardware Sequence Flags Table".) See "6. AC Waveforms for Data Polling during Embedded Algorithm Operations" in s SWITCHING WAVEFORMS for the Data Polling timing specifications and diagrams.
10. DQ6 Toggle Bit I
The CSR2930800BA also feature the "Toggle Bit I" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See "7. AC Waveforms for Toggle Bit I during Embedded Algorithm Operations" in s SWITCHING WAVEFORMS for the Toggle Bit I timing specifications and diagrams.
11. DQ5 Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the devices under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2 mA). 21
CSR2930800BA-90
The OE and WE pins will control the output disable functions as described in "CSR2930800BA User Bus Operations Tables (BYTE = VIH and BYTE = VIL)" in s DEVICE BUS OPERATION. The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the DQ5 bit will indicate a "1." Please note that this is not a device failure condition since the devices were incorrectly used. If this occurs, reset the device with command sequence.
12. DQ3 Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low ("0"), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See "Hardware Sequence Flags Table".
13. DQ2 Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic "1" at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows: For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also "Hardware Sequence Flags Table" and "15. DQ2 vs. DQ6" in s SWITCHING WAVEFORMS. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) *1 Erase-Suspend Program DQ7 DQ7 0 1 DQ7 DQ6 Toggle Toggle 1 Toggle *1 DQ2 1 Toggle Toggle 1 *2
*1: Performing successive read operations from any address will cause DQ6 to toggle. *2: Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. 22
CSR2930800BA-90
14. RY/BY Ready/Busy
The CSR2930800BA provide a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands. If the CSR2930800BA are placed in an Erase Suspend mode, the RY/BY output will be high. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. Refer to "8. RY/BY Timing Diagram during Program/Erase Operations" and "9. RESET/RY/BY Timing Diagram" in s SWITCHING WAVEFORMS for a detailed timing diagram. The RY/ BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
15. Byte/Word Configuration
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the CSR2930800BA devices. When this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ0 to DQ15. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit and DQ8 to DQ14 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ0 to DQ7 and the DQ8 to DQ15 bits are ignored. Refer to "10. Timing Diagram for Word Mode Configuration" and "11. Timing Diagram for BYTE Mode Configuration" SWITCHING WAVEFORMS for the timing diagram. and "12. BYTE Timing Diagram for Write Operations" in s
16. Data Protection
The CSR2930800BA are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the devices automatically reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise.
17. Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 2.3 V. If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
18. Write Pulse "Glitch" Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
19. Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one.
20. Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 23
CSR2930800BA-90
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with respect to Ground All pins except A9, OE, RESET *1 VCC *1 A9, OE, and RESET *
2
Symbol
Rating Min -55 -40 -0.5 -0.5 -0.5 Max +125 +85 VCC+0.5 +5.5 +13.0
Unit C C V V V
*1: Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, inputs may undershoot VSS to - 2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V. During voltage transitions, outputs may overshoot to VCC +2.0 V for periods of up to 20 ns. *2: Minimum DC input voltage on A9, OE and RESET pins is -0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9, OE and RESET pins is +13.0 V which may overshoot to 14.0 V for periods of up to 20 ns. Voltage difference between input voltage and supply voltage (VIN - VCC) do not exceed 9 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING RANGES
Parameter Ambient Temperature Supply Voltages Symbol TA VCC Conditions CSR2930800BA-90 Value Min -40 +2.7 Max +85 +3.6 Unit C V
Note: Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their our representatives beforehand.
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CSR2930800BA-90
s MAXIMUM OVERSHOOT /MAXIMUM UNDERSHOOT
+0.6 V -0.5 V -2.0 V
20 ns
20 ns
20 ns
Figure 1
Maximum Undershoot Waveform
20 ns
V CC +2.0 V V CC +0.5 V +2.0 V
20 ns 20 ns
Figure 2
Maximum Overshoot Waveform 1
20 ns
+14.0 V +13.0 V V CC +0.5 V
20 ns 20 ns
*: This waveform is applied for A9, OE, and RESET.
Figure 3
Maximum Overshoot Waveform 2
25
CSR2930800BA-90
s DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Symbol ILI ILO ILIT Test Conditions VIN = VSS to VCC, VCC = VCC Max VOUT = VSS to VCC, VCC = VCC Max VCC = VCC Max A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f=10 MHz VCC Active Current *
1
Value Min -1.0 -1.0 -- Byte Word Byte Word -- -- -- -- -- -- -0.5 2.0 11.5 -- 2.4 VCC-0.4 2.3 Max +1.0 +1.0 35 22 25 12 15 35 5 5 5 0.6 VCC+0.3 12.5 0.45 -- -- 2.5
Unit A A A mA mA mA A A A V V V V V V V
ICC1 CE = VIL, OE = VIH, f=5 MHz
VCC Active Current *2 VCC Current (Standby) VCC Current (Standby, Reset) VCC Current (Automatic Sleep Mode) *3 Input Low Level Input High Level Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 Output Low Voltage Level Output High Voltage Level Low VCC Lock-Out Voltage
ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO
CE = VIL, OE = VIH VCC = VCC Max, CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max, RESET = VSS 0.3 V VCC = VCC Max, CE = VSS 0.3 V, RESET = VCC 0.3 V VIN = VCC 0.3 V or VSS 0.3 V -- -- -- IOL = 4.0 mA, VCC = VCC Min IOH = -2.0 mA, VCC = VCC Min IOH = -100 A --
*1: The ICC current listed includes both the DC operating current and the frequency dependent component (at 10 MHz). *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4: (VID - VCC) do not exceed 9 V.
26
CSR2930800BA-90
s AC CHARACTERISTICS
* Read Only Operations Characteristics Parameter Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE to BYTE Switching Low or High Symbol
JEDEC
Standard
Value * Test Setup Min -- CE = VIL OE = VIL OE = VIL -- -- -- -- -- -- 90 -- -- -- -- -- 0 -- -- tRC -90 Max -- 90 90 35 30 30 -- 20 5 ns ns ns ns ns ns ns s ns Unit
tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- --
tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH
Note: Test Conditions: Output Load: 1 TTL gate and 100 pF (CSR2930800BA-90) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or 3.0 V Timing measurement reference level Input: 1.5 V Output:1.5 V
VCC IN3064 or Equivalent Device Under Test 6.2 k CL Diodes = IN3064 or Equivalent
2.7 k
Notes : CL = 100 pF including jig capacitance (CSR2930800BA-90) Figure 4 Test Conditions
27
CSR2930800BA-90
* Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Symbol
JEDEC
Standard
-90 Min 90 0 45 45 0 0 0 10 0 0 0 0 0 0 45 45 25 25 50 500 4 100 4 4 0 500 200 35 Typ 8 1 Max 35 90 35
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s sec s ns s s s s ns ns ns ns ns ns ns
tAVAV tAVWL tWLAX tDVWH tWHDX -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- --
2 1
tWC tAS tAH tDS tDH tOES tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVLHT tWPP tOESP tCSP tRB tRP tRH tFLQZ tFHQV tBUSY tEOE
Read Recover Time Before Write Read Recover Time Before Write CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Byte Programming Operation Sector Erase Operation * VCC Setup Time Rise Time to VID *2 Voltage Transition Time * Write Pulse Width *2 OE Setup Time to WE Active *2 CE Setup Time to WE Active * Recover Time From RY/BY RESET Pulse Width RESET Hold Time Before Read BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Program/Erase Valid to RY/BY Delay
Delay Time from Embedded Output Enable
2
-- -- -- -- -- -- -- -- -- -- --
*1: This does not include the preprogramming time. *2: This timing is for Sector Protection operation. 28
CSR2930800BA-90
s ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle Limit Min -- -- -- -- 100,000 Typ 1 16 8 8.4 -- Max 10 360 300 25 -- Unit s s s s cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead --
s PIN CAPACITANCE
* TSOP(I) Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 7.5 8.0 10.0 Max 9.5 10.0 13.0 Unit pF pF pF
Notes: * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipula by output capacitance. * FBGA Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 7.5 8.0 10.0 Max 9.5 10.0 13.0 Unit pF pF pF
Notes: * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipula by output capacitance. * SCSP Parameter Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 7.5 8.0 10.0 Max 9.5 10.0 13.0 Unit pF pF pF
Notes: * Test conditions TA = +25C, f = 1.0 MHz * DQ15/A-1 pin capacitance is stipula by output capacitance.
29
CSR2930800BA-90
s SWITCHING WAVEFORMS
* Key to Switching Waveforms
WAVEFORM
INPUTS Must Be Steady May Change from H to L May Change from L to H "H" or "L" Any Change Permitted Does Not Apply
OUTPUTS Will Be Steady Will Be Changing from H to L Will Be Changing from L to H Changing State Unknown Center Line is HighImpedance "Off" State
1. AC Waveforms for Read Operations
tRC
Address
Address Stable
tACC
CE
tOE tDF
OE
tOEH
WE
tCE
Outputs
High-Z
Output Valid
High-Z
30
CSR2930800BA-90
2. AC Waveforms for Hardware Reset/Read Operations
tRC
Address
tACC tRH
Address Stable
RESET
tOH
Outputs
High-Z
Output Valid
3. AC Waveforms for Alternate WE Controlled Program Operations
3rd Bus Cycle Address
555h tWC tAS PA tAH
Data Polling
PA tRC
CE
tCS tCH tCE
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tOH
Data
A0h
PD
DQ7
DOUT
DOUT
Notes: * * * * * *
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
31
CSR2930800BA-90
4. AC Waveforms for Alternate CE Controlled Program Operations
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CE
tDS tDH
Data
A0h
PD
DQ7
DOUT
Notes: * * * * * *
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
32
CSR2930800BA-90
5. AC Waveforms Chip/Sector Erase Operations
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
CE
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS AAh
tDH 55h 80h AAh 55h
10h for Chip Erase 10h/ 30h
Data
tVCS
VCC
*: SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase. Note: These waveforms are for the x16 mode. The addresses differ from x8 mode.
33
CSR2930800BA-90
6. AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
* DQ7
Data DQ7 DQ7 = Valid Data High-Z
tWHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6 = Output Flag tEOE
DQ0 to DQ6 Valid Data
High-Z
*: DQ7 = Valid Data (The device has completed the Embedded operation).
7. AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ6
Data
DQ6 = Toggle
DQ6 = Toggle
tOE
DQ6 = Stop Toggling
Valid
*: DQ6 stops toggling (The device has completed the Embedded operation).
34
CSR2930800BA-90
8. RY/BY Timing Diagram during Program/Erase Operations
CE
Rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
9. RESET/RY/BY Timing Diagram
WE
RESET
tRP tRB
RY/BY
tREADY
10. Timing Diagram for Word Mode Configuration
CE
BYTE
Data Output (DQ0 to DQ7) tELFH tFHQV A-1 DQ15 Data Output (DQ0 to DQ14)
DQ0 to DQ14
DQ15/A-1
35
CSR2930800BA-90
11. Timing Diagram for Byte Mode Configuration
CE
BYTE
tELFL
DQ0 to DQ14
Data Output (DQ0 to DQ14)
Data Output (DQ0 to DQ7)
DQ15/A-1
DQ15 tFLQZ
A-1
12. BYTE Timing Diagram for Write Operations
Falling edge of the last write signal
CE or WE
BYTE
tSET (tAS)
Input Valid
tHOLD (tAH)
36
CSR2930800BA-90
13. AC Waveforms for Sector Protection Timing Diagram
A18, A17, A16 A15, A14 A13, A12 A0
SAX
SAY
A1
A6
12 V 3V A9
tVLHT
12 V 3V OE
tVLHT tWPP tVLHT tVLHT
WE
tOESP
CE
tCSP
Data
tVCS tOE
01h
VCC
SAX : Sector Address for initial sector SAY : Sector Address for next sector Note: A-1 is VIL on byte mode.
37
CSR2930800BA-90
14. Temporary Sector Unprotection Timing Diagram
VCC tVCS 12 V 3V RESET
tVIDR tVLHT
3V
CE
WE
tVLHT RY/BY
Program or Erase Command Sequence
tVLHT
Unprotection Period
15. DQ2 vs. DQ6
Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Toggle DQ2 and DQ6 with OE or CE
Note
DQ2 is read from the erase-suspended sector.
38
CSR2930800BA-90
16. Extended Sector Protection Timing Diagram
VCC
tVCS
RESET tVIDR Add
tVLHT
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE TIME-OUT
WE
Data
60h
60h
40h tOE
01h
60h
SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-Out window = 150 s (Min)
39
CSR2930800BA-90
s FLOW CHART
1. Embedded ProgramTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Program Command Sequence (See below)
Data Polling Device
Increment Address
No
Last Address ? Yes
Programming Completed
Program Command Sequence* (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
*: The sequence is applied for x 16 mode. The addresses differ from x 8 mode.
40
CSR2930800BA-90
2. Embedded EraseTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Erase Command Sequece (See below) Data Polling or Toggle Bit Successfully Completed
Erasure Completed Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): 555h/AAh
Chip Erase Command Sequence* (Address/Command): 555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address/30h
Sector Address/30h
Additional sector erase commands are optional.
Sector Address/30h
*: The sequence is applied for x 16 mode. The addresses differ from x 8 mode.
41
CSR2930800BA-90
3. Data Polling Algorithm
Start
Read (DQ 0 to DQ 7) Addr. = VA
DQ 7 = Data? No No DQ 5 = 1? Yes Read (DQ 0 to DQ 7) Addr. = VA
Yes
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = Any of the sector addresses within the sector not being protected during chip erase
DQ 7 = Data? No Fail
Yes
Pass
Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
42
CSR2930800BA-90
4. Toggle Bit Algorithm
Start
Read (DQ 0 to DQ 7) Addr. = "H" or "L"
DQ 6 = Toggle ? Yes No DQ 5 = 1? Yes Read (DQ 0 to DQ 7) Addr. = VA
No
DQ 6 = Toggle ? Yes Fail
No
Pass
Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1".
43
CSR2930800BA-90
5. Sector Protection Algorithm
Start
Setup Sector Addr. (A18, A17, A16, A15, A14, A13, A12)
PLSCNT = 1
OE = V ID, A 9 = V ID, A 6 = CE = V IL, RESET = V IH A 0 = V IL, A 1 = V IH Activate WE Pulse
Increment PLSCNT
Time out 100 s
WE = V IH, CE = OE = V IL (A 9 should remain V ID)
Read from Sector (Addr. = SA, A 0 = V IL, A 1 = V IH, A 6 = V IL)* No No PLSCNT = 25? Yes Remove V ID from A 9 Write Reset Command Data = 01H? Yes Yes Protect Another Sector? No Device Failed Remove V ID from A 9 Write Reset Command
Sector Protection Completed
*: A-1 is V IL on byte mode.
44
CSR2930800BA-90
6. Temporary Sector Unprotection Algorithm
Start
RESET = VID (Note 1)
Perform Erase or Program Operations
RESET = VIH
Temporary Sector Unprotection Completed (Note 2)
Notes: * All protected sectors are unprotected. * All previously protected sectors are protected once again.
45
CSR2930800BA-90
7. Extended Sector Protection Algorithm
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 s
Device is Operating in Temporary Sector Unprotection Mode
No
Extended Sector Protection Entry? Yes To Setup Sector Protection Write XXXh/60h
PLSCNT = 1
To Sector Protection Write SPA/60h (A0 = VIL, A1 = VIH, A6 = VIL)
Increment PLSCNT
Time Out 150 s
To Verify Sector Protection Write SPA/40h (A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Address
Read from Sector Address (A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01h? Yes Protection Other Sector ? No Remove VID from RESET Write Reset Command Yes
Device Failed
Sector Protection Completed
46
CSR2930800BA-90
8. Embedded ProgramTM Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
Set Fast Mode
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling Device
Verify Byte? Yes No
No
In Fast Program
Increment Address
Last Address ? Yes Programming Completed
XXXh/90h Reset Fast Mode XXXh/F0h
*: The sequence is applied for x 16 mode. The addresses differ from x 8 mode.
47
CSR2930800BA-90
s ORDERING INFORMATION
Standard Products
Standard products are available in several packages. The order number is formed by a combination of:
CSR2930800
B
A
-90
PFTN
PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Normal Bend PBT-= 48-Ball Fine Pitch Ball Grid Array Package (FBGA:BGA-48P-M12) PW-= 48-Ball Super Chip Size Package (SCSP)
SPEED OPTION See Product Selector Guide Device Revision BOOT CODE SECTOR ARCHITECTURE B = Bottom sector
DEVICE NUMBER/DESCRIPTION CSR2930800 8Mega-bit (1M x 8-Bit or 512K x 16-Bit) CMOS Flash Memory 3.0 V-only Read, Program, and Erase
48
CSR2930800BA-90
s PACKAGE DIMENSIONS
48-pin plastic TSOP(1) (FPT-48P-M19)
LEAD No.
1 48
Note 1: *Resin protrusion. (Each side: 0.15(.006)Max) Note 2: Pins width and pins thickness include plating thickness.
INDEX
Details of "A" part
0.25(.010)
0~8
0.600.15 (.024.006)
24
25
20.000.20 (.787.008) * 18.400.20 (.724.008)
* 12.000.20 (.472.008) 11.50REF (.453)
1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height) 0.100.05 (.004.002) (Stand off height)
"A"
0.10(.004)
0.50(.020) TYP 0.17 -0.08 .007 -.003
+0.03 +.001
0.220.05 (.009.002)
0.10(.004)
M
C
2001 FUJITSU LIMITED F48029S-c-4-5
Dimensions in mm (inches)
48-pin plastic FBGA (BGA-48P-M12)
9.000.20(.354.008) 1.05 -0.10 .041 -.004 (Mounting height) 0.380.10(.015.004) (Stand off)
+0.15 +.006
5.60(.220) 0.80(.031)TYP
6 5 INDEX 6.000.20 (.236.008) 4 4.00(.157) 3 2 1
H C0.25(.010)
G
F
E
D
C
B
A
M
48-o0.450.10 (48-o.018.004)
o0.08(.003)
0.10(.004)
C
2001 FUJITSU LIMITED B48012S-c-3-3
Dimensions in mm (inches)
49
CSR2930800BA-90
48-pin plastic SCSP (WLP-48P-M03)
(3.50=0.50x7) ((.138=.020x7)) Y 0.50(.020) TYP
7.060.10(.278.004)
(0.13SQ) ((.005SQ)) 3.520.10 (.139.004) (2.50=0.50x5) ((.098=.020x5))
(INDEX)
(0.25(.010) 0.50(.020) TYP
(2.25) ((.089)) 4-O0.13(4-O.005)
INDEX AREA (LASER MARKING)
X
1.00(.039) Max.
48-O0.350.10 (48-O.014.004)
0.08(.003)
M
XYZ
Z
0.10(.004) Z
0.25(.010) Min.
(Stand off)
C
2001 FUJITSU LIMITED W48003S-c-1-1
Dimensions in mm (inches)
50

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